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Make optoelectronic packaging and testing simple and efficient

Terawan Tech.,co.LTD

Hotline

86-755-32843656

Tera2060 1~12.5G SFP+ BERT

BASIC INFO



Description

The Tera2060-2 is 6 channel 1.25G/2.5G/5G/6G/8G/10G/12.5G BERT system, could provide 1.25G/2.5G/5G/6G/8G/10G/12.5G optical module test/debug solution for R&D engineer and manufacture.

The Tera2060 could work mother board with daughter card. Replaceable daughter card for SFP/SFP+ module volume testing.

?  9V power supply, could support remote control in lab.

?  Support different PRBS pattern, include PRBS7/PRBS11/PRBS15/PRBS23/PRBS31

?  Could parallel test 6pcs SFP/SFP+ module: 1.25G/2.5G/5G/6G/8G/10G/12.5G  

?  Support real-time BER report for 6pcs SFP/SFP+

?  Support Alarm-history function,  record alarm history at long-term testing

?  Both port have trig clock output for the eye diagram monitor.

 

Tera2060 Physical Interface

Power supply

Tera2060 adapter 9V DC power supply. Power supply must not exceed 9V, higher than 9V will damage the analyzer permanently.


Console Interface

Tera2060 use the COM for the remote control and test function.


Traffic Interface

Current Tera2060 have two type daughter card option for SFP and RF connector, Also could support HDMI and USB 3.0 Type C connector :

1st option is standard 6 optical lane SFP cage.




Parameter

Min

Typical

Max

Unit

備注

Bit rate

1.25

 

12.5

Gb/s

 

Amplitue

200

 

800

mV

 

JitterP-P

 

 

22.5

Ps

 

JitterRMS

 

2.0

3.0

Ps

**

Rising/Fall time

18

 

 

Ps

 

Pre-emp

 

 

4

dB

 

Input

20

 

1000

mV

 

Input Jitter Tolerance

 

0.5

 

UI

均衡最優

Input

 

 

12

dB

 

Power supply

5

8.5

9

V(DC)

 

Power dissipation

 

 

15

W

 

Temperature

-5

 

55

oC

 

Store

-10

 

70

oC

 

Humility

5

 

90

%

Non-Condensing

RF interface

K2.92mm),Compliant SMA

 


**notes: Measurements based on PRBS^23-1 data at 9.95 Gbps,.

Trigger Clock Interface

 Tera2140 have two trigger clock for the both group port:

1st trigger clock is for 6 channel, support 1.25G/2.5G/8G/10.3G/11.3G eye diagram test

2nd trigger clock is for the 6channel, support 3.125G/6G/9G/12.5G eye diagram test


10.7 Gbps output eye diagram

2060  RF port output eye


GUI

The BERT system could be control by computer,RF BERT and optical BERT system GUI as following

  

Operate procedure 

More test or operate procedure please contact sales: Sales@terawan.com

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Company: Terawan Tech.,co.LTD

Contact: luyuanyuan

Tel: 86-755-32843656

Phone: 15817448677

E-mail: Sales@terawan.com

Address: Building C, 3rd Floor, Futian Industrial Zone, No. 19 Guanlan Avenue, Longhua District, Shenzhen City china